Metal oxide semiconductor transistors (MOS) are important basic electronics components in semiconductor technology. MOS devices can be substantially divided into three types: (1) N-channel MOS (NMOS), (2) P-channel MOS (PMOS), and (3) Complementary MOS (CMOS). A CMOS is composed by an NMOS and a PMOS. Such kind of transistors, wherein the ON/OFF state are determined by the values of gate voltages, and the values of the current flowing through the transistor channel are determined by the source voltages, are called field effect transistors (FET), and therefore NMOS and PMOS are called NFET and PFET, respectively.
There are resistances in a transistor device exist within the material itself, the junction of two kinds of materials, or a specific structure of the transistor . . . , and so on. These resistances have significant influences on the performances of transistor elements. The main resistances of a transistor include the channel resistance formed between the drain region and the source region, and the other resistances commonly known as extrinsic resists. As the MOS device 1 shown in FIG. 1, there is an extrinsic resistance including a contact resistance 12 formed between a source 11 and a conductive metal layer 12, the internal resistance of the conductive metal layer 12 itself (metal resist), and an extension resistance formed between a gate 13 and the source (or drain) 11. When the MOS manufacturing process proceeds to a smaller line width (for example, from 90 nm to 22 nm), the shorter the length of the channel, the smaller the channel resistance will be, but vice versa the extrinsic resistance. Accordingly, it has become an important subject to reduce the extrinsic resistance for manufacturing MOS devices.
The extrinsic resistance is dominated by the contact resistance, and the value of the contact resistance is mainly determined by the following equation (1) to the resistivity ρc:
                              ρ          c                ∝                  exp          ⁡                      [                                                            4                  ⁢                                                                          ⁢                                      πϕ                    B                                                                    q                  ⁢                                                                          ⁢                  h                                            ⁢                                                                    m                    *                                          ɛ                      Si                                                                            N                    D                                                                        ]                                              (        1        )            Among numerical members in equation (1), metal-semiconductor work function ΦB, semiconductor doping ND, and effective carrier mass m* are variables, while other symbols represent well-known constants and will not be described here.
Conventional MOS structures utilize metal layers as drain/source contacts. The metal layers are usually made of silicide, such as nickel silicide, titanium silicide, etc. However, since the metal layer is in direct contact with the semiconductor layer (MS contact), there are defects found in the contact surface between the two layers, resulting in that the work function can not be decreased, which is a fermi level pinning causing the contact resistance to be remained in a high level. To solve this problem, S. Datta et al (2014 Symposium on VLSI Technology Digest of Technical Papers) add another insulating layer (Insulator) in the traditional metal/semiconductor junction, making it a MIS structure, such that the work function is effectively reduced.
However, although the above-described MIS structure effectively reduces the contact resistance of a NFET, it is difficult to select a suitable insulating layer to reduce the contact resistance of a PFET and thus the overall contact resistance of a CMOS still cannot be reduced effectively, which becomes the problem to be resolved. U.S. Pat. No. 7,274,055 discloses the concept of choosing suitable materials to reduce the contact resistance. However, in the structure disclosed by this patent, a polysilicon capping layer is used for connecting drain/source SiGe layer and the metal layer. Subject to the material properties of silicon itself, the contact resistance still cannot be reduced to be meeting a demand or requirement level.